This invention relates to a nonvolatile semiconductor memory device that can be operated at high speed with low voltage and to its manufacturing method.
Now the prior art nonvolatile semiconductor memory device is explained with reference to the attached drawings.
FIG. 33 illustrates a schematic cross sectional view of the prior art nonvolatile semiconductor memory device. Referring now to FIG. 33, a floating gate electrode 203 is formed on the semiconductor substrate 201 via a first dielectric film 202; on this floating gate 203, a control gate electrode 205 is formed via a second dielectric film 204; a source region 206 and a drain region 207 are formed in the semiconductor substrate 201 on both side regions of the floating gate electrode 203.
In the nonvolatile semiconductor memory device of such a structure, hot electrons are generated near the drain region 207 where a positive voltage is applied, and the generated hot electrons are injected into the floating gate electrode 203 when data is written. In order to improve the writing performance, a voltage higher than that applied to the source region 206 is applied to the drain region 207. Then since the electric field in parallel to the substrate is raised, the efficiency of generating hot electrons is raised as well. The floating gate electrode 203 is mounted in parallel to the direction in which hot electrons run. Thus, in order to inject hot electrons into the floating gate electrode 203, which are generated in the channel region under the floating gate electrode 203, the hot electrons must be scattered to change their direction of movement.
Further, for higher probability of carrier injection, high voltage must be applied to the control gate electrode 205 for raising the potential bias between the floating gate and the drain, in order to electrically pull hot electrons toward the floating gate electrode 203.
However, in the prior art nonvolatile semiconductor memory device, if the drain voltage is raised to increase the hot electron generation efficiency, the potential between the floating gate and the drain falls and then the hot electron injection efficiency falls as well.
Meanwhile, if the voltage applied to the control gate electrode 205 is raised, the electric field along the substrate is attenuated and then the hot electron generation efficiency falls.
Namely, there is a problem that the writing speed cannot be raised only by applying high voltage to either the control gate electrode 205 or the drain region 207.
It is, therefore, an object of the present invention to provide a nonvolatile semiconductor memory device that can attain high carrier injection efficiency even at low voltage when hot carriers are injected into the floating gate electrode.
To attain the above object, the present invention proposes a drain region structure in which the injected carriers are subject to an external electric force toward the floating gate electrode when the carriers are injected into the floating gate electrode.
A first nonvolatile semiconductor memory device according to the present invention comprises: a floating gate electrode, formed on a semiconductor region, for storing carriers injected from the semiconductor region; a control gate electrode for controlling a quantity of stored carriers by applying a predetermined voltage to the floating gate electrode; and a source region formed in the semiconductor region on one of side regions of the floating gate electrode and control gate electrode and a drain region formed in the semiconductor region on the other of side regions thereof; wherein the drain region creates an electric field so that the carriers injected to the floating gate electrode are subject to an external force having an element directed from the semiconductor region to the floating gate electrode.
According to the first nonvolatile semiconductor memory device, the drain region creates an electric field so that the carriers injected to the floating gate electrode are subject to an external force directed from the semiconductor region toward the floating gate electrode. Then if the voltage applied to the drain region is relatively low during the writing operation, the hot carrier injection efficiency is improved since the hot carriers generated under the floating gate electrode are pulled by the floating gate electrode.
To be more specific, a second nonvolatile semiconductor memory device according to the present invention comprises: a floating gate electrode formed ion a semiconductor region via a first dielectric film; a control gate electrode capacitively coupled with the floating gate electrode via a second dielectric film; and a source region formed in the semiconductor region on one of side regions of the floating gate electrode and control gate electrode and a drain region formed in the semiconductor region on the other of side regions thereof; wherein the end of the drain region faced with the source region has an embedded drain region extending toward the source region without reaching the surface of the semiconductor region, and a channel region is formed near the surface of the semiconductor region above the embedded drain region in.
According to the second nonvolatile semiconductor memory device, the end of the drain region on the side of the source region has an embedded drain region extending toward the source region without reaching the surface of the semiconductor region. As a result, the channel region is formed near the surface of the semiconductor region above this embedded drain region. Then during the writing operation the carriers injected to the floating gate electrode are subject to an external force having a force element directed from the semiconductor region toward the floating gate electrode, and if the voltage applied to the drain region is relatively low the hot carriers generated near under the floating gate electrode are pulled to the floating gate electrode. As a result, the hot carrier injection efficiency is improved.
Preferably, the second nonvolatile semiconductor memory device further comprises an embedded region adjacent upper area that is formed in an upper part of the embedded drain region in the semiconductor region and has a conduction type opposite to that of the drain region. Then, if both embedded drain region and the drain region are n-type, for example, the boundary between the embedded drain region and the embedded region adjacent upper area becomes a pn junction. The electric field between the embedded drain region and the embedded region adjacent upper area is augmented when a bias voltage is applied to the substrate. As a result, the carrier injection efficiency is further raised.
In this case, it is preferable that the impurity concentration in the embedded region adjacent upper area is higher than that in the semiconductor region.
Otherwise in this case, the embedded drain region has the conduction type opposite to that of the drain region and an impurity concentration lower than that in the embedded region adjacent upper area. It becomes thereby possible to raise the carrier injection efficiency even if the embedded drain region has the conduction type opposite to that of the drain region.
In the second nonvolatile semiconductor memory device according to the invention, it is preferable that the embedded drain region has the same conduction type as that of the drain region and an impurity concentration lower than that in the drain region. Then it becomes possible to move more hot carriers generated between the floating gate electrode and the embedded drain region toward the surface of the semiconductor region.
In the second nonvolatile semiconductor memory device, it is preferable that it further comprises an embedded region adjacent lower area that is formed in the lower part of the embedded drain region in the semiconductor region and has a conduction type opposite to that of the drain region. Then it becomes possible to enhance the substrate bias effect.
In this case, it is preferable that the impurity concentration in the embedded region adjacent lower area is higher than that in the semiconductor region.
In the second nonvolatile semiconductor memory device, it is preferable that the semiconductor region has a stepped portion, the floating gate electrode is formed astride the stepped portion, and the drain region and embedded drain region are formed under the lower side of the the stepped portion. In this way, the electric field is strengthened in the neighborhood of the lower corner of the stepped portion area when a voltage is applied to the control gate electrode and the drain region. Since this concentration of the electric field provides a high electric field toward the drain region in the channel region, the hot electron generation efficiency is improved.
In the second nonvolatile semiconductor memory device, it is preferable that the carriers located in the channel region under the floating gate are subject to a force element of the electric field perpendicular to the surface of the semiconductor region when a predetermined voltage is applied to the control gate electrode or the drain region.
Further in the second nonvolatile semiconductor memory device, it is preferable that the control gate electrode is formed above the floating gate electrode.
Yet further in the second nonvolatile semiconductor memory device, it is preferable that the control gate electrode is formed on the semiconductor region in the vicinity of the side of the floating gate electrode.
A nonvolatile semiconductor memory device manufacturing method according to the present invention comprises the steps of: forming an embedded drain region by injecting a first impurity in a semiconductor region so that the top of the embedded drain region does not reach the main surface of the semiconductor region; forming a gate dielectric film on the main surface of the semiconductor region; forming first and second gate electrodes on the gate dielectric film so that the first gate electrode capacitively coupled with the second electrode is located above the embedded drain region; and injecting a second impurity into the semiconductor region, using the first and second gate electrodes as masks, to form a source region in the semiconductor region on one of side regions of the first and second gate electrodes, and a drain region in the other of the side regions thereof under the first gate electrode so that it contacts the embedded drain region.
According to the manufacturing method for the nonvolatile semiconductor memory device, the embedded drain region is formed inside the semiconductor region by injecting the first impurity into the semiconductor region so that its top does not reach the main surface of the semiconductor region. Later, the drain region is formed so as to contact the embedded drain region under the first gate electrode on the side region of the first and second gate electrodes. As a result, the second nonvolatile semiconductor memory device can be provided with reliability.
It is preferable that the nonvolatile semiconductor memory device manufacturing method further comprises the step of forming an embedded region adjacent upper area above a formation region to be formed as the embedded drain region in the semiconductor region by selectively injecting a third impurity having a conduction type opposite to that of the second impurity into the semiconductor region prior to the formation of the gate electrode.
It is preferable that the nonvolatile semiconductor memory device manufacturing method further comprises the step of forming an embedded region adjacent lower area under a formation region to be formed as the embedded drain region in the semiconductor region by selectively injecting a third impurity having a conduction type opposite to that of the second impurity into the semiconductor region prior to the formation of the gate electrode.
It is preferable that in the nonvolatile semiconductor memory device manufacturing method the step of forming the gate electrode includes the step of forming the second gate electrode above the first gate electrode via a capacitance dielectric film.
It is preferable that in the nonvolatile semiconductor memory device manufacturing method the step of forming the gate electrode includes the step of forming the first gate electrode on the side of the second gate electrode via a capacitance dielectric film.
It is preferable that the nonvolatile semiconductor memory device manufacturing method further comprises the step of forming a stepped portion above a formation region to be formed as the embedded drain region in the semiconductor region prior to the gate dielectric film formation step, so that the lower stage of the stepped portion is the side of the drain region, wherein the first gate electrode is formed astride the stepped portion in the gate electrode formation step.
It is preferable that the nonvolatile semiconductor memory device manufacturing method further comprises the step of forming a stepped portion above a formation region to be formed as the embedded drain region in the semiconductor region prior to the embedded drain region formation step, so that the lower stage of the stepped portion is the side of the drain region, wherein the first gate electrode is formed astride the stepped portion in the gate electrode formation step.
Further, it is preferable that in the nonvolatile semiconductor memory device manufacturing method the conduction type of the first impurity is the same as that of the second impurity and the concentration of the first impurity is lower than that of the second impurity.
Yet further, it is preferable that in the nonvolatile semiconductor memory device manufacturing method the conduction type of the first impurity is different from that of the second impurity and the concentration of the first impurity is lower than that of the third impurity.